ALGAL DIVERSITY IN MIDSTREAM OF THE ACHANKOVIL RIVER DURING MONSOON AND POST MONSOON SEASON

Algae are simple organisms whose size ranges from microscopic to macroscopic large seaweeds over thirty meters long. The study examined the algal diversity in the midstream of the Achankovil River. Pandalm is located in the central point of the Achankovil River. Water samples were collected during the monsoon and post monsoon seasons. Samples were collected in the early morning; phytoplanktonic forms were gathered by plankton net. The exploration identified the presence of 41 algal genera pertaining to the classes of Chlorophyceae, Bacillariyophyceae, Cyanophyceae and Euglenophyceae. The pollution-indicating species increased in post monsoon season in comparison to monsoon season of the river and larger numbers of algal species are reported during monsoon season

Non-volatile spin wave majority gate at the nanoscale

A spin wave majority fork-like structure with feature size of 40\,nm, is presented and investigated, through micromagnetic simulations. The structure consists of three merging out-of-plane magnetization spin wave buses and four magneto-electric cells serving as three inputs and an output. The information of the logic signals is encoded in the phase of the transmitted spin waves and subsequently stored as direction of magnetization of the magneto-electric cells upon detection. The minimum dimensions of the structure that produce an operational majority gate are identified. For all input combinations, the detection scheme employed manages to capture the majority phase result of the spin wave interference and ignore all reflection effects induced by the geometry of the structure

Sterile inflammation enhances ECM degradation in integrin β1 KO embryonic skin

Epidermal knockout of integrin β1 results in complete disorganization of the basement membrane (BM), resulting in neonatal lethality. Here, we report that this disorganization is exacerbated by an early embryonic inflammatory response involving the recruitment of tissue-resident and monocyte-derived macrophages to the dermal-epidermal junction, associated with increased matrix metalloproteinase activity. Remarkably, the skin barrier in the integrin β1 knockout animals is intact, suggesting that this inflammatory response is initiated in a sterile environment. We demonstrate that the molecular mechanism involves de novo expression of integrin αvβ6 in the basal epidermal cells, which activates a TGF-β1 driven inflammatory cascade resulting in upregulation of dermal NF-κB in a Tenascin C-dependent manner. Importantly, treatment of β1 KO embryos in utero with small molecule inhibitors of TGF-βR1 and NF-κB results in marked rescue of the BM defects and amelioration of immune response, revealing an unconventional immuno-protective role for integrin β1 during BM remodeling

BTI impact on logical gates in nano-scale CMOS technology

status: publishe

Compilation for Delay Impact Minimization in VLIW Embedded Systems

Tomorrow’s embedded devices need to run high resolution multimedia as well as need to support multistandard wireless systems which require an enormous computational complexity with a very low energy consumption and very high performance constraints. In this context, the register file is one of the key sources of power consumption and performance bottleneck, and its inappropriate design and management can severely affect the performance of the system. In this paper, we present a new compilation approach to mitigate the performance implications of technology variation in the shared register file in upcoming embedded VLIW architectures with several processing units. The compilation approach is based on a redefined register assignment policy and a set of architectural modifications to this device. Experimental results show up to a 67% performance improvement with our technique

Energy-Aware Compilation and Hardware Design for VLIW Embedded Systems

Tomorrow's embedded devices need to run multimedia applications demanding high computational power with low energy consumption constraints. In this context, the register file is a key source of power consumption and its inappropriate design and management severely affects system power. In this paper, we present a new approach to reduce the energy of shared register files in forthcoming embedded VLIW processors running real-life applications up to 60% without performance penalty. This approach relies on limited hardware extensions and a compiler-based energy-aware register assignment algorithm to deactivate at run-time parts of the register file (i.e., sub-banks) in an independent way

Resolving the Memory Bottleneck for Single Supply Near-Threshold Computing

This paper focuses on a review of state-of-the-art memory designs and new design methods for near-threshold computing (NTC). In particular, it presents new ways to design reliable low-voltage NTC memories cost-effectively by reusing available cell libraries, or by adding a digital wrapper around existing commercially available memories. The approach is based on modeling at system level supported by silicon measurement on a test chip in a 40nm low-power processing technology. Advanced monitoring, control and run-time error mitigation schemes enable the operation of these memories at the same optimal near-Vt voltage level as the digital logic. Reliability degradation is thus overcome and this opens the way to solve the memory bottleneck in NTC systems. Starting from the available 40 nm silicon measurements, the analysis is extended to future 14 and 10 nm technology nodes

Compiler-Driven Leakage Energy Reduction

Abstract. Tomorrow's embedded devices need to run high-resolution multimedia applications which need an enormous computational complexity with a very low energy consumption constraint. In this context, the register file is one of the key sources of power consumption and its inappropriate design and management can severely affect the performance of the system. In this paper, we present a new approach to reduce the energy of the shared register file in upcoming embedded VLIW architectures with several processing units. Energy savings up to a 60% can be obtained in the register file without any performance penalty. It is based on a set of hardware extensions and a compiler-based energy-aware register assignment algorithm that enable the de/activation of parts of the register file (i.e. sub-banks) in an independent way at run-time, which can be easily included in these embedded architectures

Joint Hardware-Software Leakage Minimization Approach for the Register File of VLIW Embedded Architectures

New applications demand very high processing power when run on embedded systems. Very Long Instruction Word (VLIW) architectures have emerged as a promising alternative to provide such processing capabilities under the given energy budget. However, in this new VLIW-based architectures, the register file is a very critical contributor to the overall power consumption and new approaches have to be proposed to reduce its power while preserving system performance. In this paper, we propose a novel joint hardware–software approach that reduces the leakage energy in the register files of these embedded VLIW architectures. This approach relies upon an energy-aware register assignment method and a hardware support that creates sub-banks in the global register file that can be switched on/off at run time. Our results indicate energy savings in the register file, after considering the overhead of the added extra hardware, up to 50% for modern multimedia embedded applications without performance degradation. We illustrate this approach using real-life applications running on these processors. We also illustrate the tradeoff between the area overhead vs. the gains in the leakage energy for the different strategies